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 IRF240
Data Sheet March 1999 File Number
1584.3
18A, 200V, 0.180 Ohm, N-Channel Power MOSFET
This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17422.
Features
* 18A, 200V * rDS(ON) = 0.180 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER IRF240 PACKAGE TO-204AE BRAND IRF240
Symbol
D
NOTE: When ordering, include the entire part number.
G
S
Packaging
JEDEC TO-204AE TOP VIEW
DRAIN (FLANGE)
SOURCE (PIN 2) GATE (PIN 1)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
IRF240
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified IRF240 200 200 18 11 72 20 125 1.0 580 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs tD(ON) tr tD(OFF) tf Qg Qgs Qgd CISS COSS CRSS LD Measured between the Contact Screw on Header that is Closer to Source and Gate Pins and Center of Die Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances
D LD G LS S
TEST CONDITIONS VGS = 0V, ID = 250A (Figure 10) VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = 20V VGS = 10V, ID = 10A (Figures 8, 9) VDS = 10V, ID = 11V (Figure 12) VDD = 100V, ID 18A, RG = 9.1, RL = 5.3 (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature
MIN 200 2.0 18 6.7 -
TYP 0.14 9.0 16 27 40 31 43 8 27 1275 500 160 5.0
MAX 4.0 25 250 100 0.180 30 60 80 60 60 -
UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH
Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
On-State Drain Current (Note 2) Gate to Source Leakage Drain to Source On Resistance Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse-Transfer Capacitance Internal Drain Inductance
VGS = 10V, ID = 18A, VDS = 0.8 x Rated BVDSS , Ig(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature
-
VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11)
-
Internal Source Inductance
LS
-
12.5
-
nH
Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
RJC RJA Free Air Operation
-
-
1.0 30
oC/W oC/W
2
IRF240
Source to Drain Diode Specifications
PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode
G D
MIN -
TYP -
MAX 18 72
UNITS A A
S
Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES:
VSD trr QRR
TJ = 25oC, ISD = 18A, VGS = 0V (Figure 13) TJ = 150oC, ISD = 18A, dISD/dt = 100A/s TJ = 150oC, ISD = 18A, dISD/dt = 100A/s
-
650 4.1
2.0 -
V ns C
2. Pulse Test: Pulse width 300s, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 2.7mH, RG = 25, peak IAS = 9A. See Figures 15 and 16.
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0
Unless Otherwise Specified
20
0.8 0.6 0.4 0.2 0
ID, DRAIN CURRENT (A)
16
12
8
4
0 0 50 100 150 25 50 75 100 125 150 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
1.0 ZJC, THERMAL IMPEDANCE 0.5
0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE PDM t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 PER UNIT BASE = RJC = 1.0oCW TJM - TC = PDM x ZJC (t) 10-4 10-3 10-2 0.1 1 10
0.01 10-5
t1, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
3
IRF240 Typical Performance Curves
100
Unless Otherwise Specified
(Continued)
40 10V
8V 9V
80s PULSE TEST
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
10s 100s 10 1ms OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 10ms 100ms DC TC = 25oC TJ = MAX RATED SINGLE PULSE 102 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 103
32 7V 24
16
VGS = 6V
1
8
5V 4V
0.1 1.0
0
0
10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V)
50
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. OUTPUT CHARACTERISTICS
40 80s PULSE TEST 32
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VGS = 10V VGS = 9V VGS = 8V
40 TJ = -55oC 32 TJ = 25oC TJ = 125oC 24 VDS > ID(ON) x RDS(ON)MAX 80s PULSE TEST 16
24
VGS = 7V VGS = 6V
16
8
VGS = 5V VGS = 4V
8
0
0
1 2 3 4 VDS , DRAIN TO SOURCE VOLTAGE (V)
5
0
0
2 4 6 8 VSD , GATE TO SOURCE VOLTAGE (V)
10
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
0.5 80s PULSE TEST NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE 0.4 ON RESISTANCE () VGS = 10V 0.3
2.5 ID = 18A VGS = 10V 2.0
1.5
0.2 VGS = 20V 0.1
1.0
0.5
0 0 20 60 40 ID , DRAIN CURRENT (A) 80 100 0 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160
NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
4
IRF240 Typical Performance Curves
1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A
Unless Otherwise Specified
(Continued)
2000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS
1.15 C, CAPACITANCE (pF)
1800
1.05
1200
CISS
0.95
800 CRSS
COSS
0.85
400
0.75 -40
0
40
80
120
160
0
0
TJ , JUNCTION TEMPERATURE (oC)
10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V)
50
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
19.0 ISD, SOURCE TO DRAIN CURRENT (A) 80s PULSE TEST gfs, TRANSCONDUCTANCE (S) 15.2 TJ = -55oC TJ = 25oC TJ = 125oC 7.6
50
20
11.4
10 TJ = 150oC TJ = 25oC
5
3.8
2
0 0 8 16 24 ID , DRAIN CURRENT (A) 32 40
1
0
0.4 0.8 1.2 1.6 VSD , SOURCE TO DRAIN VOLTAGE (V)
2.0
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20 VGS, GATE TO SOURCE VOLTAGE (V) ID = 18A 16 VDS = 40V 12 VDS = 100V VDS = 160V
8
4
0 0 12 24 36 48 60 Qg , TOTAL GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
5
IRF240 Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
-
0V
IAS 0.01
0 tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) tr RL VDS 90%
tOFF td(OFF) tf 90%
+
RG DUT
-
VDD
0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR
VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS
12V BATTERY
0.2F
50k 0.3F
G
DUT
0
Ig(REF) 0 IG CURRENT SAMPLING RESISTOR
S VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
6
IRF240
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
7


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